The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Oct. 27, 1998
Applicant:
Inventor:
Toru Inoue, Tokyo, JP;
Assignee:
Oki Electric Industry Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
With this invention, the clock skew of logical integrated circuits is suppressed. To do this, with this invention, chip integrated circuit forming areas are divided into rectangular blocks with the same dimensions, clock drivers are placed in each block, and these clock drivers are connected with basic logic circuits and dummy loads. The total basic logic circuit count and dummy load count is made the same for all clock drivers. This allows the load of each clock driver to be made the same, so generation of clock skew can be suppressed.