The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
May. 05, 1998
Keiko Ohsawa, Kawasaki, JP;
Terunobu Maruyama, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A cell arrangement evaluating method for predicting a wiring density based on only a cell arranging result prior to initiation of any wiring programs so as to easily perform wiring condition evaluation based on the wiring density within a short time. Two cells to be connected by wiring are selected, and a rectangular region is obtained in which the pins of the two cells to be connected are diagonal verfexes. The probability of wiring between the pins to be connected passing through a certain grid point of wiring grid is calculated. A proportion of the rectangular region occupying each evaluation unit grid is calculated, and then, for each evaluation unit grid, an index for an increase of a wiring density made by the factor of the wiring in the evaluation unit grid is calculated. Then, for each evaluation unit grid, the sum of indexes calculated for all the wiring lines among the cells as a wiring density in the evaluation unit grid is calculated. The cell arrangement evaluation method is used for designing an integrated circuit such an LSI or a circuit on a printed circuit board.