The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Jul. 31, 1998
Anthony Gus Aipperspach, Rochester, MN (US);
Leland Leslie Day, Rochester, MN (US);
Paul Allen Ganfield, Rochester, MN (US);
Charles Luther Johnson, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.