The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Jul. 30, 1998
Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
Steven R. Cole, San Jose, CA (US);
Russell T. Baca, Fremont, CA (US);
Siemens Information and Communication Networks, Inc., Boca Raton, FL (US);
Abstract
A synchronization circuit (,) includes three flip-flops responsive to a common clock signal (CLK,). The input to the first flip-flop (,) represents the least significant bit (LSB) of a counter (,) included within a first clock domain. The CLK,signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop (,), and the second flip-flop output is provided as input to the third flip-flop (,). An exclusive-or (XOR) gate (,) generates a synchronization signal in response to outputs of the second and third flip-flops (,). The synchronization signal is usable within the second clock domain and activate for one period of CLK,subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of data inputs is stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize the data inputs.