The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Dec. 09, 1998
Geoffrey S. Strongin, Austin, TX (US);
Qadeer A. Qureshi, Round Rock, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
It has been discovered that a method and system can be produced which will, among other things, provide data processing systems having memory controllers with the ability to look ahead and intelligently schedule accesses to system memory. A method and system which improve data processing system memory access. The method and system provide a first-stage origin-sensitive memory access request reordering device, and a second-stage destination-sensitive memory access request reordering device operably coupled to said first-stage origin-sensitive memory access request reordering device. The first-stage origin-sensitive memory access request reordering device receives memory access requests having associated origin information, and reorders the memory access requests based upon the associated origin information. The first-stage origin-sensitive memory access request reordering device delivers to the second-stage destination-sensitive memory access request reordering device one or more memory access requests which the first-stage origin-sensitive memory access request reordering device has deemed to be the requests which should be next executed. The second-stage destination-sensitive memory access request reordering device receives such one or more reordered memory access requests from the first stage and, in conjunction with the state of various system memory devices, again reorders the requests on the basis of the state of various system memory devices, prior to executing the one or more requests.