The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Dec. 17, 1998
Yi-Ming Ku, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A shared peripheral controller including a primary bus interface, a primary bus first register, a shared bus interface, and a control unit. The primary bus interface is adapted to receive an operation via a primary bus, such as an ISA bus, from a first processor, such as a PCI-to-ISA bus bridge. The shared bus interface is adapted to communicate with a first shared peripheral, such as a real time clock, via a shared bus. The control unit is coupled to the primary bus interface and configured to detect a first segment of a first operation issued by the first processor to the first shared peripheral. The control unit is further configured to buffer the first segment in the primary bus first register until the control unit detects a second segment of the first operation whereupon the control unit is configured to issue the first and second segments of the first operation to the first shared peripheral in consecutive cycles of the shared bus. In the preferred embodiment, the controller further includes a secondary bus first register and a secondary bus interface that is adapted to receive an operation via a secondary bus, such as a 68000 bus, from a second processor, such as a service processor. In this embodiment, the control unit is coupled to the secondary bus interface and configured to detect a first segment of a second operation that is issued by the second processor and further adapted to buffer the second operation's first segment in the secondary bus first register until the control unit detects a second segment of the second operation whereupon the second operation's second segment, the control unit issues the second operation's first and second segments to the first shared peripheral in consecutive cycles of the shared bus.