The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2001

Filed:

Nov. 24, 1998
Applicant:
Inventors:

James R. Magro, Austin, TX (US);

Daniel P. Mann, Austin, TX (US);

Floyd Goodrich, III, Portland, OR (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 ; G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 3/00 ; G06F 1/300 ;
Abstract

A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.


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