The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Jun. 11, 1998
Jae-Jin Shin, Kwangmyong, KR;
Kyung-Geun Lee, Sungnam, KR;
Dan-Keun Sung, Daejon, KR;
Jeong-Won Heo, Daejon, KR;
Sung-Hyuk Byun, Siheung, KR;
Ju-Yong Lee, Daegoo, KR;
Jin-Woo Yang, Busan, KR;
SamSung Electronics Co., Ltd., Suwon, KR;
Abstract
A controller for the logical buffer depth in ATM switching system and a method for determining the logical queue depth, using the back-pressure signal and the occupied buffer depth information and supporting the P classes, are disclosed. The controller includes Routing Table Element making tag for routing of input cell; Input Buffer storing the cell that a tag is attached to in said routing table element; Switch fabric that reads the cell from said input buffer and then switches it to the output port; and Input buffer controller controlling the logical queue size in said input buffer. And the method for determining the logical queue depth includes the steps of calculating the back-pressure signal occurrence rate b,of the ith class; calculating the back-pressure signal occurrence threshold rate b,of the ith class; calculating the buffer depth T,of the logical queue of the ith class; calculating threshold values T,T,of the two buffer depths of the ith class; calculating the buffer size L,of the logical queue of the ith class; calculating the empty area size D,(j=1, 2, 3, L, P) of logical queues for the number of p classes.