Integrated circuit memory devices having an improved wafer burn-in test capability through independent operational control of a memory cell array and related methods of testing same

Abstract

Integrated circuit memory devices and methods of testing same use a word line selection unit generate address signals to selectively activate word lines of a memory cell array in response to a plurality of first input signals. In addition, a write and read control unit independently generates an operation control signal in response to a second input signal that is used to place the memory cell array into a “read mode” or a “write mode.” Because the operation control signal is generated independent from the word line selection unit, a wafer burn-in test write operation can be performed on all memory cells of the memory cell array. Moreover, the independence of the write and read control unit can allow the memory cell array to be enabled for a read operation before initiating the read operation through the word line selection unit thereby avoiding any potential race condition.