Nonvolatile semiconductor memory device equipped with verification circuit for identifying the address of a defective cell

Abstract

A nonvolatile semiconductor memory device has an array of memory cells in columns and rows, and has word lines and bit lines provided in orthogonal directions, the memory cells for each column sharing one of the bit lines, and the memory cells for each row sharing one of the word lines. The memory device includes a plurality of subblocks of N page buffers where N is a given positive integer, the N page buffers for each subblock temporarily storing data bits that are written to or erased from N memory cells at a time in the memory array in response to a selected one of the word lines. A verify/output circuit produces, in response to signals output by the plurality of subblocks of N page buffers, a verify status of each of the respective subblocks that indicates whether the data bits are properly written to or erased from the N memory cells, the verify/output circuit outputting the verify status of at least one of the plurality of subblocks to an external device.