Register transfer level (rtl) based scan insertion for integrated circuit design processes

Abstract

A design-level description of a circuit is processed to incorporate testability functions in the form of scan chains. The design-level description may be a Register Transfer Level (RTL) description in accordance with the VHDL standard. The design-level description includes processes describing operations of the circuit. The processes are analyzed to identify data carriers in the design-level description which correspond to flip-flops or other specified elements in the circuit. The specified elements are organized into scan chains, which are then allocated to appropriate modules of the circuit. Scan ordering and scan insertion operations are performed separately on each of the modules. The scan ordering operation is based on functional relationships between the data carriers in the processes associated with the modules. The functional relationships can include both word-level and bit-level dependencies. The scan insertion operation involves inserting scan assignment statements into the processes. The modified design-level descriptions of the modules are separately synthesized to generate gate-level descriptions of the circuit modules, such that the overall circuit includes the appropriate scan chains.