The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2001

Filed:

Sep. 04, 1998
Applicant:
Inventor:

Alan F. Hendrickson, Austin, TX (US);

Assignee:

DSP Group, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 2/730 ;
U.S. Cl.
CPC ...
H04L 2/730 ;
Abstract

In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, a receiver PN clock, and a slow-tracking logic. The slow-tracking logic temporarily advances and delays the receiver PN clock by a small shift and checks if either advancing or delaying consistently results in improved correlations. If so, the slow-tracking logic adjusts the receiver PN clock accordingly. The slow tracking logic preferably also includes a counter that maintains an integrated total of the adjustments to the receiver clock. The integrated total adjustment is used to determine the long-term adjustment.


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