Semiconductor memory device decoder

Abstract

A semiconductor memory device includes a plurality of memory cell array blocks, an address transition detecting pulse generator to generate address transition detecting pulse signals by detecting the transition of a plurality of addresses, a global row decoder having a plurality of groups of pre-decoders and a main decoder to generate a plurality of global word line signals of a plurality of memory cell array blocks by decoding the plurality of addresses, and a plurality of block row decoders having a plurality of decoding cells to respond to block control signals for selecting a plurality of memory cell array blocks and a plurality of pulse control signals combined with the address transition detecting pulse signals to output a plurality of global word line signals generated by the global row decoder as a plurality of local word line signals. A plurality of the decoding cells of a plurality of the block row decoders comprises switching transistors or other means to switch the global word line signals into local word line signals in response to a first state of the pulse control signals, and inactive means, e.g. one or more transistors, to put the local word line signals into its inactive state in response to a second state of the pulse control signals, thereby reducing the number of transistors to make up of the decoder for efficient layout.