Integrated circuit memory devices having adjacent input/output buffers and shift blocks

Abstract

An integrated circuit memory device is provided which includes input buffers placed adjacent an associated input shift block rather than displaced with intervening regions, such as a pad block, between the buffer and the shift block. As a result, a single input clock line may be provided which can support both the input buffers and the shift block. The single line may also provide less loading allowing a lower power driver in the memory device's clock circuit. In addition, the input clock line may avoid routing through the pad block which in turn may reduce noise on the input clock line from signals in the pad block. The output buffers and associated shift block may also be located adjacent each other on the on the integrated circuit memory device to allow similar benefits on the output clock side of the memory device. Accordingly, memory devices are provided which may consume less power and be reduced in size. The integrated circuit memory device may be a Rambus DRAM.