The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2001
Filed:
Jan. 14, 1998
Applicant:
Inventors:
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 ;
U.S. Cl.
CPC ...
G09G 3/36 ;
Abstract
A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd,is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd,through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd,through Ckdn. The output circuit outputs one of the correction subject signal Ckd,and the delayed signals Ckd,trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.