The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2001
Filed:
Sep. 05, 2000
Bjoern Jelonnek, Ulm, DE;
Detlev Nyenhuis, Sibesse, DE;
Robert Bosch GmbH, Stuttgart, DE;
Abstract
The present invention is directed to a sigma-delta D-A converter (,) with N stages, in which the nth stage, where n=1, 2, 3 . . . N, comprises a first adder (,) which adds a use signal x(k) (,) with an error signal err,(k−1) to an input signal e,(k) (,), a quantizer (,) which quantizes the input signal e,(k) (,) to an output signal y,(k) (,) according to a predetermined quantization function, and a second adder (,) which adds the input signal e,(k) (,) with the inverted output signal y,(k) to x,(k) (,), and supplies it to a delay device (,) which sends the signal x,(k) (,) to the first adder (,) as an error signal err,(k−1) with a delay by a clock period. For this purpose, an amount reducer (,) is provided between the second adder (,) and the delay device (,), which amount reducer (,) leaves the signal x,(k) (,) unchanged when x,(k)=0 and otherwise lowers the amount |x,(k)| of the signal x,(k) (,) by at least a smallest representable numerical unit, wherein the quantization function of the quantizer (,) of the nth stage of the sigma-delta D-A converter (,) is expressed as follows: