The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2001

Filed:

May. 07, 1999
Applicant:
Inventors:

Coralyn S. Gauvin, Colorado Springs, CO (US);

William K. Petty, Colorado Springs, CO (US);

Brian K. Herbert, Colorado Springs, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 1/126 ;
U.S. Cl.
CPC ...
H03H 1/126 ;
Abstract

A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.


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