Hardware design for majority voting, and testing and maintenance of majority voting

Abstract

The invention relates to majority voting testing. A number of input signals are monitored individually by separate monitors, one monitor for each signal. Each monitor generates a control signal representing the status of the monitored signal. The generated control signals are sent to a level control unit. The level control unit controls the input levels to a majority voter according to the control signals. Instead of signals that are faulty, the level control unit selects signals of specific logical levels to be forwarded to the majority logic. The logical levels of these so called replacement signals are selected such that the replacement signals do not interfere with the remaining correct signals. Furthermore, the majority voted output signal is monitored so as to selectively generate an alarm. The voting functionality is tested by stopping input signals according to a first procedure, thus generating an alarm. By stopping input signals according to a second procedure, an alarm is avoided.