The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2001

Filed:

Apr. 20, 1999
Applicant:
Inventors:

Jean-Marc Dortu, Munich, DE;

Albert M. Chu, Essex, VT (US);

Frank Ferraiolo, Essex, VT (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract

A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected across an input node and an output node. A delay element is connected to the input node, the delay element for providing a predetermined delay value to an input signal from the input node to provide a delayed input signal. A phase comparator is connected to the output node and the delay element for comparing phase differences between an output signal and the delayed input signal and for outputting the control signal to the delay line such that the delay line provides the predetermined delay value to the delay line across the input and output nodes.


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Dortu, Jean-Marc. (2001). Delay element using a delay locked loop (U.S. Patent No. 6252443). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6252443

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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