The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2001
Filed:
Sep. 17, 1998
William A. Shelly, Phoenix, AZ (US);
Charles P. Ryan, Phoenix, AZ (US);
Bull HN Information Systems Inc., Waltham, MA (US);
Abstract
Interactions among multiple processors (,) are exhaustively tested. A master processor (,) retrieves test information for a set of tests from a test table (,). It then enters a series of embedded loops, with one loop for each of the tested processors (,). A cycle delay count for each of the tested processors (,) is incremented (,) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (,). In each such test (,), the master processor (,) sets up (,) each of the other processors (,) being tested. This setup (,) specifies the delay count and the code for that processor (,) to execute. When each processor (,) is setup (,), it waits (,) for a synchronize interrupt (,). When all processors (,) have been setup (,), the master processor (,) issues (,) the synchronize interrupt signal (,). Each processor (,) then starts traces (,) and delays (,) the specified number of cycles. After the delay, the processor (,) executes its test code (,).