High speed raid cache controller using accelerated graphics port

Abstract

The high-speed, multi-device PCI bus communication system of the invention includes a host CPU and a chip set for connecting the host CPU to a first, low speed PCI bus. The chip set has an accelerated graphics port. A VLSI device such as a RAID cache controller includes two PCI interfaces for communicating with second and third, higher speed PCI buses, and includes an accelerated graphics interface for communicating with the accelerated graphics port. A first PCI bridge provides for communication between the accelerated graphics interface and the first PCI interface; and a second PCI bridge provides for communication between the accelerated graphics interface and the second PCI interface. A dedicated communication bus connects the accelerated graphics interface to the accelerated graphics port. A RAM port can connect the VLSI device to external RAM. The system provides for coupling multiple (e.g., six) high speed SCSI devices to the second and third buses, operating at 66 MHz or more, and for coupling utility devices (e.g., ISA devices) to the first PCI bus operating at lesser speeds, e.g., 33 MHz. Communication between the host CPU and the RAID controller is performed over the dedicated communication bus directly through the chip set AGP, thereby freeing up the first, low-speed PCI bus for use with lower-speed utility devices and not impacting other RAID data traffic.