The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2001

Filed:

Dec. 31, 1998
Applicant:
Inventors:

Cem Hocaoglu, Port Jefferson Station, NY (US);

Robert J. Graves, Pelham, MA (US);

Arthur C. Sanderson, Williamstown, MA (US);

Raj Subbu, Troy, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/900 ;
U.S. Cl.
CPC ...
G06F 1/900 ;
Abstract

A Virtual Design Module (VDM) used in a networked design environment generates manufactured product designs that are near optimal in terms of cost and production cycle time by using design data files containing alternative parts and manufacturers information. Numerous product design alternatives are considered and evaluated in terms of design-manufacturing-parts-supplier feasibility and real-time information on cost and production cycle time for realization. The VDM generates a population of new designs with appropriate board design information to allow for design-manufacturer-supplier decision making and determines the feasibility of each member of the current generation of designs and rejects designs that are not feasible. The VDM triggers Mobile Software Agents (MSA) that obtain data for parts availability, cost, lead time and manufacturer data for manufacturing availability, cost and lead time for each feasible member of the current generation of designs and return the data. In one application for printed circuit board design, the VDM evaluates each member of the current generation of designs by calculating cost, lead-time and value using a J function. The VDM then improves board designs through selection and use of board design modifiers. The process continues until optimized designs are obtained. Optimized board designs are output as results to an operator.


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