The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2001
Filed:
Dec. 15, 1999
Applicant:
Inventors:
John J. Silver, Monument, CO (US);
Julian C. Gradinariu, Colorado Springs, CO (US);
Bogdan I. Georgescu, Colorado Springs, CO (US);
Keith A. Ford, Colorado Springs, CO (US);
Sean B. Mulholland, Colorado Springs, CO (US);
Danny L. Rose, Monument, CO (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract
A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.