The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2001

Filed:

Oct. 01, 1998
Applicant:
Inventors:

Homi E. Nariman, Austin, TX (US);

H. Jim Fulford, Austin, TX (US);

Charles E. May, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/941 ;
U.S. Cl.
CPC ...
H01L 2/941 ;
Abstract

A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).


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