The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2001
Filed:
Apr. 02, 1999
Chien-Sheng Hsieh, Taipei, TW;
Wei-Ray Lin, Taipei, TW;
Fu-Liang Yang, Tainan, TW;
Erik S. Jeng, Hsinchu, TW;
Bor-Ru Sheu, Hsinch, TW;
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.