Efficient data loading scheme to minimize pci bus arbitrations delays and wait states

Abstract

A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register. If the target ready signal is asserted too frequently for the first holding register to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the first holding register to the output holding register. If the target ready signal is asserted relatively infrequently and the first holding register has sufficient time to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the second holding register to the output holding register.