The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2001
Filed:
Feb. 06, 1998
P. Keith Muller, San Diego, CA (US);
Kit M. Chow, Carlsbad, CA (US);
Michael W. Meyer, Encinitas, CA (US);
Alan P. Adamson, San Diego, CA (US);
NCR Corporation, Dayton, OH (US);
Abstract
A highly-scalable parallel processing computer system architecture is described. The parallel processing system comprises a plurality of compute nodes for executing applications, a plurality of I/O nodes, each communicatively coupled to a plurality of storage resources, and an interconnect fabric providing communication between any of the compute nodes and any of the I/O nodes. The interconnect fabric comprises a network for connecting the compute nodes and the I/O nodes, the network comprising a plurality of switch nodes arranged into more than g(log,N) switch node stages, wherein b is a total number of switch node input/output ports, and g(x) indicates a ceiling function providing the smallest integer not less than the argument x, the switch node stages thereby providing a plurality of paths between any network input port and network output port.