The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2001
Filed:
Apr. 08, 1999
Ignacio A. Linares, Plano, TX (US);
Donald H. Topper, III, Van Alstyne, TX (US);
Dale L. Reynolds, Krugerville, TX (US);
Alcatel USA Sourcing, L.P., Plano, TX (US);
Abstract
A peripheral device isolator (,) is provided which consists of an insulating material (,) having a first conductive area (,) on a top surface and a second conductive area (,) on a bottom surface. A transient voltage suppressor (,) provides an electrical connection between the first conductive area (,) and second conductive area (,) through a first lead (,) and a second lead (,). When the peripheral device isolator (,) is placed between an internal peripheral device (,), having a common logic and chassis ground, and a host frame (,), having a host system frame ground (,), an electrical path for a voltage spike occurring on the internal peripheral device (,) is provided so that the voltage spike can be diverted away from host system logic ground (,) and into host system frame/safety ground (,). Under normal circumstances, the transient voltage suppressor (,) is in a non-conductive state so that the separation of the host system logic ground (,) and the host system frame/safety ground (,) is maintained. The transient voltage suppressor (,) is in a conductive state only upon sensing a voltage spike on the chassis of the internal peripheral device (,).