Output buffer for a low voltage differential signaling receiver

Abstract

A three-state CMOS output buffer (,), having protective circuitry and an output node (OUT) connected to a bus, prevents damage to a connected integrated circuit when the bus voltage exceeds a power supply reference voltage (V,). A final output stage of the output buffer (,) includes a first pull-up transistor (QP,), a clamping transistor (QN,), and a pull-down transistor (QN,). A half-pass circuit (QN,) blocks the output voltage from propagating through the final output stage to damage the output buffer (,) when the output voltage applied to the output node (OUT) exceeds the supply voltage. The protective circuitry uses a clamping circuit (,), a switching circuit (,) and a backgate bias circuit (,) to prevent a leakage path between the output node (OUT) and the power supply reference (V,) through the source/bulk junction of biased transistors in the output buffer (,). The clamping circuit (,) turns the pull-up transistor (QP,) fully off when the output buffer (,) is enabled and an input signal (V,) is high and when the output buffer (,) is disabled. When the output buffer (,) is disabled, the switching circuit (,) turns the clamping circuit (,) off prior to turning the half pass circuit (QN,) and the pull-up transistor (QP,) off. The backgate bias circuit (,) provides a bias voltage equivalent to the power supply reference voltage (V,), as long as the bus voltage is not higher than the power supply reference voltage (V,), and bias equivalent to the bus voltage, when the bus voltage exceeds the power supply reference voltage (V,). Thus, the protective circuitry provides protection without a glitch of bus voltage propagating through the final output stage.