Methods of fabricating field effect transistors by first forming heavily doped source/drain regions and then forming lightly doped source/drain regions

Abstract

Heavily doped source/drain regions are formed in an integrated circuit substrate prior to forming lightly doped source/drain regions in the integrated circuit substrate. High temperature thermal processing preferably is carried out prior to forming the lightly doped source/drain regions in the integrated circuit substrate. Reduced short channel effects may thereby be obtained while still achieving shallow junctions. More specifically, an insulated gate electrode comprising polysilicon is formed on an integrated circuit substrate. The insulated gate electrode is oxidized. A gate spacer is formed on the oxidized sidewalls of the insulated gate electrode. Heavily doped source/drain regions are formed in the integrated circuit substrate by first implanting ions into the integrated circuit substrate using the insulated gate electrode and the gate spacer on the oxidized sidewalls of the insulated gate electrode as an implantation mask. The gate spacer is removed from the oxidized sidewalls of the insulated gate electrode after performing the step of forming heavily doped source/drain regions in the integrated circuit substrate. Finally, lightly doped source/drain regions, that are lightly doped relative to the heavily doped source/drain regions, are formed in the integrated circuit substrate. The lightly doped source/drain regions are formed by implanting ions into the integrated circuit substrate using the insulated gate electrode as an implantation mask, after performing the step of removing the gate spacers from the oxidized sidewalls of the insulated gate electrode.