The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2001

Filed:

Aug. 04, 1998
Applicant:
Inventors:

Qing Yang, Wakefield, RI (US);

Yiming Hu, Kingston, RI (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

A data storage system includes redundant write caches, a disk controller and an array of disks. One of the redundant write caches is a primary write cache of RAM or NVRAM, and another is a backup write cache having a hybrid memory structure of a relatively small amount of NVRAM in combination with a cache-disk space mapped to disk. The cache-disk space may be located on a single disk within the disk array, or distributed over a number of the plurality of disks in the array. In one embodiment, the array of disks can may be configured as a RAID architecture. The data storage system of the present invention preferably employs a conventional, fast-write-fast-read primary write cache and a non-volatile, hybrid memory backup write cache. The redundant write caches are asymmetric since the primary write cache and the backup write cache have different sizes and structures. The system is relatively inexpensive since the amount NVRAM in the backup cache is relatively small, ranging from hundreds of KB to several MB, and the cost of the disk space for the cache-disk space is significantly less than a large amount of NVRAM. Advantageously, the caching arrangement of the present invention has a significant reliability advantage over conventional single NVRAM write caches, and a cost advantage over dual-copy NVRAM caches. In addition, the prevent invention provides a cost-effective architecture for very large write caches capable of masking the effects of small writes for high-end data storage systems that would otherwise have to use dual-copy, identical NVRAM caches.


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