The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2001

Filed:

Nov. 21, 1996
Applicant:
Inventors:

William L. Devanney, Menlo Park, CA (US);

Robert J. Proebsting, Los Altos Hill, CA (US);

Assignee:

Integrated Device Technology, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/336 ; G06F 3/00 ; H03K 1/9003 ; H03K 1/90175 ;
U.S. Cl.
CPC ...
G06F 1/336 ; G06F 3/00 ; H03K 1/9003 ; H03K 1/90175 ;
Abstract

A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word. The complement next data word is instead communicated onto the bus along with an indicator signal to indicate that a complement data word is communicated onto the bus. Consequently, no more than half the bits of the bus ever change state at a time, thus reducing the switching noise associated with communicating data words onto the bus. A bus interface includes a spatially distributed tally circuit having a respective portion thereof in close proximity with a respective output circuit for each respective bit of the data word. The tally circuit determines whether at least a certain number of bits within the next word differ from corresponding bits within the present bus state. The spatially distributed nature is particularly advantageous for accommodating an extremely wide bus, such as a 424-bit bus. In various embodiments, the tally circuit includes a summing node for accumulating an incremental signal for each bit of a group of bits within the next word which differs from a corresponding bit within the present bus state.


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