Contacted cell array configuration for erasable and programmable semiconductor memories

Abstract

A contacted array of programmable and erasable semiconductor memory devices. Each of the memory devices has a split gate structure, including a source region, a drain region, a channel extending between the source and drain regions, a floating gate extending over a portion of the channel with a first dielectric layer therebetween, a control gate extending over a portion of the floating gate through a second dielectric layer, and a program gate extending above the floating gate with a dielectric layer therebetween. The program gate forms a capacitor with the floating gate with a coupling ratio sufficient to couple a voltage at least as high as the drain voltage to the floating gate, thereby establishing a high voltage at a point in the channel between the control gate and the floating gate and ensuring a high hot-electron injection towards the floating gate.