The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
May. 20, 1999
Hideaki Uemura, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
According to one embodiment, a master-slave flip-flip circuit (MS-FF) (,) includes master input transfer gate (,) connected to the input of a master latch portion (,) and a slave input transfer gate (,) connected to the input of a slave latch portion (,). A clock generating circuit (,) includes a first inverter (,-,) that provides an inverted clock signal CB,and a second inverter (,-,) that provides a non-inverted clock signal C,. The clock signals C,and CB,are provided to the slave input transfer gate (,). The clock signals C,and CB,are further provided to the master input transfer gate (,) through clock lines (,-,) and (,-,) which have a parasitic resistances R,and R,. The parasitic resistances R,and R,delay the C,and CB,signals and thereby provides a delayed inverted clock signal CB,and a delayed non-inverted clock signal C,to the master input transfer gate (,). By utilizing a clock generating circuit formed out of two inverters (,-,) and (,-,), the area of the MS-FF (,) can be reduced, and a smaller sized MS-FF circuit can be realized.