Phase locked loop

Abstract

A hybrid phase locked loop employs both analog and digital circuitry. A digital to analog converter (DAC) provides a current output signal in conjunction with a current controlled oscillator (ICO). The hybrid phase locked loop employs the digital circuitry, among other reasons, to assist in generating an optimal feedback frequency signal before the loop of the hybrid phase locked loop is closed. The hybrid phase locked loop intelligently employs appropriate switching in strategically placed portions of the hybrid phase locked loop to ensure stable operation once the loop of the hybrid phase locked loop is closed. The hybrid phase locked loop employs baseline components in certain embodiments of the invention. These baseline components are those whose component values may vary significantly as a function of operating conditions, environmental perturbations, and which have relatively relaxed tolerances/precisions. The present implementation of a hybrid phase locked loop, as described in the invention, is capable of operating using a wide variety of components having relaxed tolerances/precisions, including intrinsic devices such as MOSFET capacitors. Such baseline components are employed in electronic devices where low cost is a rigid design constraint; the present invention is appropriate for such low cost applications.