The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
Jul. 31, 1998
Applicant:
Inventor:
Stephen J. Bassett, Fort Collins, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/704 ; H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/704 ; H01L 2/362 ;
Abstract
Semiconductor die pad design consisting of an I/O cell where the outside bond site is connected to the cell's active signal, the second inside bond site is discrete and connected to one of the I/O power supplies Vdd or Vss, and the third inside bond site is discrete and connected to the compliment of the second pad site. The I/O cell design is universal to traditional wire-bonding assemblies and flip-chip assemblies.
Bassett, Stephen. (2001). Universal i/o pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly (U.S. Patent No. 6242814). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6242814
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile