The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2001

Filed:

Oct. 04, 1999
Applicant:
Inventors:

Abu-Hena Mostafa Kamal, Sunnyvale, CA (US);

Amjad Obeidat, San Francisco, CA (US);

Assignee:

National Semiconductor Corp., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

Process for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that reduces the risk of grooving and agglomeration of cobalt silicide layer, as well as boron penetration into a gate oxide layer. The process includes providing a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron dopant (BF,or B,) and nitrogen ions (N,) are implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure, implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi,layer on the silicon gate layer and to thermally activate the implanted boron. Also included is a process where a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer is first provided, followed by the implantation of nitrogen into the silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron is implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure and implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi,layer and to thermally activate the implanted boron.


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