The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
Jan. 05, 1999
Mark S. Rodder, University Park, TX (US);
Douglas T. Grider, McKinney, TX (US);
Katherine Violette, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (,) having a first region (,) and a second region (,). The first region (,) and the second region (,) include a first channel region (,) and a second channel region (,), respectively. A first gate (,) is formed proximate the first channel region (,) and is separated from the substrate (,) by a portion of a primary insulation layer (,). A second gate (,) is formed proximate the second channel region (,) and is separated from the substrate by a portion of the primary insulation layer (,). A dopant layer (,) is then formed outwardly of the substrate (,) proximate the first region (,) and the second region (,). The dopant layer (,) proximate the first region (,) is implanted with a first dopant (,). The dopant layer (,) proximate the second region (,) is implanted with a second dopant (,). A portion of the first dopant (,) in the dopant layer (,) is diffused into the substrate (,) proximate the first region (,) to form a first shallow doped region (,), and a portion of the second dopant (,) in the dopant layer (,) is diffused into the substrate (,) proximate the second region (,) to form a second shallow doped region (,). The first shallow doped region (,) may form a source and a drain for a first shallow junction transistor (,) and the second shallow doped region (,) may form a source and a drain for a second shallow junction transistor (,).