Configuration logic within a pci compliant bus interface unit which can be selectively disconnected from a clocking source to conserve power

Abstract

A computer having a bus interface unit coupled between a CPU bus and a PCI bus and/or a bus interface unit coupled between a PCI bus and memory and or I/O space. The clocking to the configuration space of the bus interface unit can be inhibited to conserve power in two ways. The first approach relies on an input/output address space containing a configuration address register. An enable bit or flag within the configuration address register can be set to allow a determination of the various PCI devices and to configure those devices linked to the PCI bus. Subsequent to computer boot up or initialization, the enable bit can be disabled to disallow further accesses to the configuration address space of the PCI device or PCI compliant bus interface unit. Disabling the enable bit further inhibits or disconnects a clocking signal from sequential logic within the configuration address space to minimize power consumption of the north bridge during its normal operation. In the second approach, the clocking to the configuration space is automatically enabled and disabled as needed by the bus interface unit to transfer data to and from its configuration registers. Removing the clocking signal, in either approach, minimizes power consumption allowing additional functions to be added to the mobile PC.