Synchronous dynamic random access memory with four-bit data prefetch

Abstract

A memory circuit for operating synchronously with a system clock signal is designed with a memory array (,) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (,) produces a select signal at a respective column select line (,) in response to a first column address signal. A plurality of sense amplifier circuits (,) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (,). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (,) is coupled to receive four data bits from four respective data lines (,) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (,) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.