The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2001

Filed:

Aug. 31, 1998
Applicant:
Inventors:

Raymond Albert Fillion, Niskayuna, NY (US);

Wolfgang Daum, Louisville, KY (US);

Ronald Frank Kolc, Cherry Hill, NJ (US);

Donald William Kuk, Albany, NY (US);

Rob Ert John Wojnarowski, Ballston Lake, NY (US);

Assignee:

General Electric Company, Schenectady NY, US;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/14 ;
U.S. Cl.
CPC ...
H05K 1/14 ;
Abstract

A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.


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