The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2001
Filed:
Aug. 13, 1997
Toshihito Shirai, Urawa, JP;
Koichi Futsuhara, Urawa, JP;
The Nippon Signal Co., Ltd., Tokyo, JP;
Abstract
The present invention relates to a fail-safe timing circuit and on-delay circuit which does not produce an erroneous output where the delay time is shortened, due to a fault. The timing circuit comprises: an oscillation circuit (,) which produces a timing output from a cathode terminal of a PUT after a predetermined time lapse from input of an input signal (V,); and a monitoring circuit (,) for monitoring for the normalcy of the oscillation circuit (,). Moreover the on-delay circuit comprises a self hold circuit (,) with an output signal (Vo) generated from the monitoring circuit (,) only when the normalcy of the oscillation circuit (,) is verified by generation of a falling signal of a cathode terminal voltage of the oscillation circuit (,), input to a second terminal (b), and the input signal (V,) input to a first terminal (a), which produces an output signal only when the two input signals are both at a higher level than a power source potential.