Clock multiplier using nonoverlapping clock pulses for waveform generation

Abstract

An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock—these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG,-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal. The pulse generator PG,is triggered by a leading edge of the reference clock, and the remaining pulse generators PG,-PGN are triggered by the trailing edge of the pulse P from the previous pulse generator. A synchronization circuit detects phase deviations between the trailing edge of the pulse PN from pulse generator PGN and the leading edge of the reference clock, and provides a corresponding phase adjustment signal used to adjust the pulse-width delay signal for at least one of the pulses P so as to achieve phase locking.