The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2001
Filed:
Nov. 18, 1998
Hiroaki Tsutsui, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In a DCFL circuit, a high-speed operation is conducted in a stable state regardless of its load capacitance. The circuit includes a buffer circuit. Added to the buffer circuit is a pull-up circuit conducting a pull-up operation for a predetermined period of time when an output potential of the circuit changes from a low level to a high level. A first EFET of the pull-up circuit includes a gate electrode connected to an output terminal of a logic stage, a drain electrode coupled with a positive power source, and a source electrode linked with a drain of a second EFET. The second EFET includes a gate electrode connected to a node linked in series to a resistor element. The resistor is coupled with an input terminal. The second EFET includes the drain electrode connected to a source electrode of the first EFET and a source electrode linked with an output terminal. Due to the operation of the pull-up circuit for a fixed period of time, the propagation delay time can be minimized without increasing the steady state current when the output potential changes from a low level to a high level.