Reduced voltage quiescent current test methodology for integrated circuits

Abstract

A method for improving the accuracy of quiescent current testing by reducing reliance on absolute quiescent current test limits. Initially, the device under test is placed into a static DC state in a traditional manner. Quiescent current is then measured with the power supply to the device set to a nominal operating voltage. Next, a fixed voltage lower than the nominal power supply voltage is applied to the integrated circuit in order to reduce the quiescent current consumed by the device. An additional quiescent current measurement is taken. The difference in quiescent current between the first and second measurements is then calculated. Additional quiescent current measurement(s) are also taken at increasing lower supply voltages. The differences in quiescent currents between each of these measurements is also calculated. After a sufficient number of measurements have been gathered, the resulting difference values are examined to determine the “linearity” of the quiescent current reduction. In an acceptable device, the lower power supply voltages cause the leakage or quiescent current inherent in the integrated circuit to decrease in a roughly exponential manner. Therefore, if the reduction in quiescent current is roughly exponential, it is generally assumed that the detected quiescent currents are a result of normal transistor effects. If the change in currents approximates a linear function, however, it is likely that the device under test contains a defect and the device is rejected.