Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices

Abstract

The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips. The etching process includes: a vertical profile etching for complete removal from the unprotected areas respectively of the first conducting layer, of the second conducting layer of the gate region; a successive etching of the dielectric interpoly layer accompanied by a considerable erosion of the dielectric film of the insulation region so as to totally uncover the first conducting layer, and a concluding etching of the first conducting layer.