The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2001
Filed:
Sep. 28, 1998
Qizhi Liu, Santa Ana, CA (US);
David Feiler, Sherman Oaks, CA (US);
Conexant Systems, Inc., Newport Beach, CA (US);
Abstract
The present invention relates to the reduction of poisoned vias in a submicron process technology semiconductor wafer by reducing the occurrence of over-etched vias through the inclusion of an etch-stop layer. Vias are created to connect conductive portions of a semiconductor wafer and if the vias are over-etched, the connection may be poor. In order to prevent the over-etching of vias, a three-step etch process is completed on a semiconductor wafer having an insulating layer, an etch-stop layer, a low dielectric constant layer, a conductive layer and a foundation layer. A via is first non-selectively etched such that the etch terminates within the insulating layer. The via is subsequently selectively etched such that the etch terminates at the etch-stop layer. Lastly, the via is again non-selectively etched through the etch-stop layer and the low dielectric constant layer such that the etch terminates at the conductive layer.