The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2001

Filed:

Mar. 29, 1999
Applicant:
Inventor:

Kuo-Tung Sung, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. A stacked gate structure is formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, and an isolation structure is formed to isolate the source region, in which a drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is form over the substrate and is patterned to remove a portion of a conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belong to a same word line. The stacked gate structure is therefore exposed.


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