Method for fabricating a dram cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern

Abstract

Provided is a method for fabricating a stacked capacitor with improved vertical and bottom etching profiles without electrical bridge between adjacent lower electrodes. Conductive layer for a lower electrode is deposited over an insulating layer whose top portion is made of a nitride etching barrier layer. During the etching of the conductive layer and subsequent overetching for lower electrode pattern, the nitride etching barrier layer serves an etching stopper and allows easier formation of polymer buildups on sidewalls of the lower electrode, more particularly on a bottom edge thereof. Resulting polymer buildups serve to prevent unacceptable bottom and sidewall etching of the lower electrode.