The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
Oct. 06, 1997
Applicant:
Inventors:
Harald Folberth, Böblingen, DE;
Joachim Keinert, Böblingen, DE;
Jürgen Koehl, Weil i.Schönbuch, DE;
Kurt Pollmann, Altdorf, DE;
Oliver Rettig, Sindelfingen, DE;
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
The present invention pertains to a design method for VLSI-chips. The chips are partitioned into segments in order to enable DRC and LVS. Thus, the memory requirements are kept below the limits of the platform used for the verification and the turnaround time is drastically reduced.
Folberth, Harald. (2001). Method and apparatus for enabling parallel layout checking of designing vlsi-chips (U.S. Patent No. 6237128). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6237128
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile